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19-2956; Rev 1; 10/09
KIT ATION EVALU E AILABL AV
Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters
General Description
The MAX1167/MAX1168 low-power, multichannel, 16bit analog-to-digital converters (ADCs) feature a successive-approximation ADC, integrated +4.096V reference, a reference buffer, an internal oscillator, automatic power-down, and a high-speed SPITM/ QSPITM/MICROWIRETM-compatible interface. The MAX1167/MAX1168 operate with a single +5V analog supply and feature a separate digital supply, allowing direct interfacing with +2.7V to +5.5V digital logic. The MAX1167/MAX1168 consume only 3.6mA (AVDD = DVDD = +5V) at 200ksps when using an external reference. AutoShutdownTM reduces the supply current to 185A at 10ksps and to less than 10A at reduced sampling rates. The MAX1167 includes a 4-channel input multiplexer, and the MAX1168 accepts up to eight analog inputs. In addition, digital signal processor (DSP)-initiated conversions are simplified with the DSP frame-sync input and output featured in the MAX1168. The MAX1168 includes a data-bit transfer input to select between 8-bit-wide or 16-bit-wide data-transfer modes. Both devices feature a scan mode that converts each channel sequentially or one channel continuously. Excellent dynamic performance and low power, combined with ease of use and an integrated reference, make the MAX1167/MAX1168 ideal for control and data-acquisition operations or for other applications with demanding power consumption and space requirements. The MAX1167 is available in a 16-pin QSOP package and the MAX1168 is available in a 24-pin QSOP package. Both devices are guaranteed over the commercial (0C to +70C) and extended (-40C to +85C) temperature ranges. Use the MAX1168 evaluation kit to evaluate the MAX1168. 16-Bit Resolution, No Missing Codes +5V Single-Supply Operation Adjustable Logic Level (+2.7V to +5.25V) Input Voltage Range: 0 to VREF Internal (+4.096V) or External (+3.8V to AVDD) Reference Internal Track/Hold, 4MHz Input Bandwidth Internal or External Clock SPI/QSPI/MICROWIRE-Compatible Serial Interface, MAX1168 Performs DSP-Initiated Conversions 8-Bit-Wide or 16-Bit-Wide Data-Transfer Mode (MAX1168 Only) 4-Channel (MAX1167) or 8-Channel (MAX1168) Input Mux Scan Mode Sequentially Converts Multiple Channels or One Channel Continuously Low Power 3.6mA at 200ksps 1.85mA at 100ksps 185A at 10ksps 0.6A in Full Power-Down Mode Small Package Size 16-Pin QSOP (MAX1167) 24-Pin QSOP (MAX1168)
Features
MAX1167/MAX1168
Applications
Motor Control Industrial Process Control Industrial I/O Modules Data-Acquisition Systems Thermocouple Measurements Accelerometer Measurements
PART MAX1167BCEE MAX1167BEEE MAX1168BCEG MAX1168BEEG
Ordering Information
TEMP RANGE 0C to +70C -40C to +85C 0C to +70C -40C to +85C PINPACKAGE 16 QSOP 16 QSOP 24 QSOP 24 QSOP INL (LSB) 3 3 3 3
Pin Configurations appear at end of data sheet. SPI/QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. AutoShutdown is a trademark of Maxim Integrated Products, Inc.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters MAX1167/MAX1168
ABSOLUTE MAXIMUM RATINGS
AVDD to AGND .........................................................-0.3V to +6V DVDD to DGND.........................................................-0.3V to +6V DGND to AGND.....................................................-0.3V to +0.3V AIN_, REF, REFCAP to AGND..................-0.3V to (AVDD + 0.3V) SCLK, CS, DSEL, DSPR, DIN to DGND ...................-0.3V to +6V DOUT, DSPX, EOC to DGND...................-0.3V to (DVDD + 0.3V) Maximum Current into Any Pin............................................50mA Continuous Power Dissipation (TA = +70C) 16-Pin QSOP (derate 8.3mW/C above +70C)...........667mW 24-Pin QSOP (derate 9.5mW/C above +70C)...........762mW Operating Temperature Ranges MAX116_ _ CE_ ..................................................0C to +70C MAX116_ _ EE_ ...............................................-40C to +85C Maximum Junction Temperature .....................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVDD = DVDD = +4.75V to +5.25V, fSCLK = 4.8MHz external clock (50% duty cycle), 24 clocks/conversion (200ksps), external VREF = +4.096V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER DC ACCURACY (Note 1) Resolution Relative Accuracy (Note 2) Differential Nonlinearity Transition Noise Offset Error Gain Error Offset Drift Gain Drift Signal-to-Noise Plus Distortion Signal-to-Noise Ratio Total Harmonic Distortion Spurious-Free Dynamic Range Full-Power Bandwidth Full-Linear Bandwidth Channel-to-Channel Isolation CONVERSION RATE Conversion Time Acquisition Time Serial Clock Frequency tCONV tACQ f SCLK Internal clock, no data transfer, single conversion (Note 5) External clock (Note 6) External clock, data transfer and conversion External clock, data transfer only 729 0.1 4.8 9 5.52 3.75 ns MHz 7.07 s SINAD SNR THD SFDR -3dB point SINAD > 85dB (Note 4) 88 (Note 3) 85 86 DYNAMIC SPECIFICATIONS (1kHz sine wave, 4.096VP-P) (Note 1) 88.5 88.5 -100 101 4 10 96 -88 dB dB dB dB MHz kHz dB (Note 3) INL DNL MAX116_B MAX116_B (16 bit, no missing codes over temperature) RMS noise External reference Internal reference 16-bit NMC 16 1.8 +0.7 0.7 0.8 0.1 0.01 1 1.2 10 0.2 3 +1.75 Bits LSB LSB LSBRMS mV %FSR ppm/C ppm/C SYMBOL CONDITIONS MIN TYP MAX UNITS
2
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Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = +4.75V to +5.25V, fSCLK = 4.8MHz external clock (50% duty cycle), 24 clocks/conversion (200ksps), external VREF = +4.096V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Internal Clock Frequency Aperture Delay Aperture Jitter SYMBOL f INTCLK tAD tAJ 8-bit-wide data-transfer mode 16-bit-wide data-transfer mode Internal clock, single conversion, 8-bit-wide data-transfer mode Sample Rate (Note 7) fS Internal clock, single conversion, 16-bitwide data-transfer mode Internal clock, scan mode, 8-bit-wide datatransfer mode (four conversions) External clock, scan mode, 16-bit-wide data-transfer mode (four conversions) Duty Cycle ANALOG INPUT (AIN_) Input Range Input Capacitance EXTERNAL REFERENCE Input Voltage Range VREF (Note 8) VAIN _ = 0 Input Current INTERNAL REFERENCE Reference Voltage Reference Short-Circuit Current Reference Temperature Coefficient Reference Wake-Up Time tRWAKE VREF = 0 0.7 DVDD 0.3 DVDD Digital inputs = 0 to DVDD 0.1 0.2 15 1 DIGITAL INPUTS (SCLK, CS, DSEL, DSPR, DIN) (DVDD = +2.7V to +5.25V) Input High Voltage Input Low Voltage Input Leakage Current Input Hysteresis Input Capacitance VIH VIL I IN VHYST CIN V V A V pF VREFIN IREFSC 4.042 4.096 13 25 5 4.136 V mA ppm/C ms IREF SCLK idle CS = DVDD, SCLK idle 3.8 34 0.1 0.1 A AVDD - 0.2 V VAIN _ CAIN _ 0 45 VREF V pF 45 4.17 3.125 89 68 103 82 55 % ksps Internal clock CONDITIONS MIN 3.2 TYP 4.0 15 <50 200.00 150.00 MAX UNITS MHz ns ps
MAX1167/MAX1168
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Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters MAX1167/MAX1168
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = +4.75V to +5.25V, fSCLK = 4.8MHz external clock (50% duty cycle), 24 clocks/conversion (200ksps), external VREF = +4.096V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER SYMBOL CONDITIONS MIN DVDD 0.4 0.8 0.4 0.1 15 4.75 2.70 200ksps 100ksps Analog Supply Current (Note 9) IAVDD 10ksps 1ksps External reference Internal reference External reference Internal reference External reference Internal reference External reference Internal reference 200ksps Digital Supply Current IDVDD DOUT = all zeros 100ksps 10ksps 1ksps CS = DVDD, SCLK = 0, DIN = 0, DSPR = DVDD Internal reference and reference buffer on between conversions Internal reference on, reference buffer off between conversions 2.7 3.6 1.4 2.7 0.14 1.8 0.014 1.7 0.87 0.45 0.045 0.005 0.66 mA 0.20 1.3 mA mA 5.25 5.25 3.3 4.2 10 TYP MAX UNITS DIGITAL OUTPUT (DOUT, DSPX, EOC) (DVDD = +2.7V to +5.25V) Output High Voltage Output Low Voltage Three-State Output Leakage Current Three-State Output Capacitance POWER SUPPLIES Analog Supply Digital Supply AVDD DVDD V V VOH VOL IL C OUT I SOURCE = 0.5mA I SINK = 10mA, DVDD = +4.75V to +5.25V I SINK = 1.6mA, DVDD = +2.7V to +5.25V CS = DVDD CS = DVDD V V A pF
Power-Down Supply Current
IAVDD + IDVDD
Shutdown Supply Current Power-Supply Rejection Ratio
IAVDD + IDVDD PSRR
CS = DVDD, SCLK = 0, DIN = 0, DSPR = DVDD, full power-down AVDD = DVDD = 4.75V to 5.25V, full-scale input (Note 10)
0.6 63
10
A dB
4
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Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters
TIMING CHARACTERISTICS (Figures 1, 2, 8, and 16)
(AVDD = DVDD = +4.75V to +5.25V, fSCLK = 4.8MHz external clock (50% duty cycle), 24 clocks/conversion (200ksps), external VREF = +4.096V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Acquisition Time SCLK to DOUT Valid CS Fall to DOUT Enable CS Rise to DOUT Disable CS Pulse Width CS to SCLK Setup CS to SCLK Hold SCLK High Pulse Width SCLK Low Pulse Width SCLK Period DIN to SCLK Setup DIN to SCLK Hold CS Falling to DSPR Rising DSPR to SCLK Falling Setup DSPR to SCLK Falling Hold SYMBOL tACQ tDO tDV tTR tCSW tCSS tCSH tCH tCL tCP tDS tDH tDF tFSS tFSH SCLK rise SCLK fall (DSP) SCLK rise SCLK fall (DSP) SCLK rise SCLK fall (DSP) SCLK rise SCLK fall (DSP) Duty cycle 45% to 55% Duty cycle 45% to 55% Conversion Data transfer Conversion Data transfer CDOUT = 30pF CDOUT = 30pF CDOUT = 30pF 100 100 0 93 50 93 50 209 50 0 100 100 0 CONDITIONS External clock (Note 6) MIN 729 50 80 80 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
MAX1167/MAX1168
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Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters MAX1167/MAX1168
TIMING CHARACTERISTICS (Figures 1, 2, 8, and 16)
(AVDD = +4.75V to +5.25V, DVDD = +2.7V to +5.25V, fSCLK = 4.8MHz external clock (50% duty cycle), 24 clocks/conversion (200ksps), external VREF = +4.096V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Acquisition Time SCLK to DOUT Valid CS Fall to DOUT Enable CS Rise to DOUT Disable CS Pulse Width CS to SCLK Setup CS to SCLK Hold SCLK High Pulse Width SCLK Low Pulse Width SCLK Period DIN to SCLK Setup DIN to SCLK Hold CS Falling to DSPR Rising DSPR to SCLK Falling Setup DSPR to SCLK Falling Hold SYMBOL tACQ tDO tDV tTR tCSW tCSS tCSH tCH tCL tCP tDS tDH tDF tFSS tFSH SCLK rise SCLK fall (DSP) SCLK rise SCLK fall (DSP) SCLK rise SCLK fall (DSP) SCLK rise SCLK fall (DSP) Duty cycle 45% to 55% Duty cycle 45% to 55% Conversion Data transfer Conversion Data transfer CDOUT = 30pF CDOUT = 30pF CDOUT = 30pF 100 100 0 93 93 93 93 209 100 0 100 100 0 CONDITIONS External clock (Note 6) MIN 729 100 100 80 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
AVDD = DVDD = +5.0V. Relative accuracy is the deviation of the analog value at any code from its theoretical value after full-scale range has been calibrated. Note 3: Offset and reference errors nulled. Note 4: DC voltage applied to on channel, and a full-scale 1kHz sine wave applied to off channels. Note 5: Conversion time is measured from the rising edge of the 8th external SCLK pulse to EOC transition minus tACQ in 8-bit data-transfer mode. Note 6: See Figures 10 and 17. Note 7: fSCLK = 4.8MHz, fINTCLK = 4.0MHz. Sample rate is calculated with the formula fs = n1 (n2 / fSCLK + n3 / fINTCLK)-1 where: n1 = number of scans, n2 = number of SCLK cycles, and n3 = number of internal clock cycles (see Figures 11-14). Note 8: Guaranteed by design; not production tested. Note 9: Internal reference and buffer are left on between conversions. Note 10: Defined as the change in the positive full scale caused by a 5% variation in the nominal supply voltage. Note 1: Note 2:
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Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters
Typical Operating Characteristics
(AVDD = DVDD = +5V, fSCLK = 4.8MHz, CDOUT = 30pF, external VREF = +4.096V, TA = +25C, unless otherwise noted.)
INL vs. CODE
MAX1167/68 toc01
MAX1167/MAX1168
DNL vs. CODE
MAX1167/68 toc02
FFT AT fAIN = 1kHz
0 -20 AMPLITUDE (dB) -40 -60 -80 -100 -120
MAX1167/68 toc03
1.5 1.0 0.5 0 -0.5 -1.0 -1.5 0 16384 32768 CODE 49152
1.5 1.0 0.5 DNL (LSB) 0 -0.5 -1.0
20
INL (LSB)
-140 -1.5 65536 0 16384 32768 CODE 49152 65536 -160 0 20 40 60 80 100 FREQUENCY (kHz)
SINAD vs. FREQUENCY
MAX1167/68 toc04
SFDR vs. FREQUENCY
MAX1167/68 toc05
THD vs. FREQUENCY
fSAMPLE = 200kbps
MAX1167/68 toc06
100 90 80 70 SINAD (dB)
120 100 80 SFDR (dB)
0 -20 -40 THD (dB) -60 -80 -100
60 50 40 30 20 10 0 0.1 1 fSAMPLE = 200kbps 10 100
60 40 20 0 0.1 1 fSAMPLE = 200ksps 10 100
-120 0.1 1 10 100 FREQUENCY (kHz)
FREQUENCY (kHz)
FREQUENCY (kHz)
SUPPLY CURRENT vs. CONVERSION RATE (EXTERNAL CLOCK)
MAX1167/68 toc07
ANALOG SUPPLY CURRENT vs. ANALOG SUPPLY VOLTAGE (INTERNAL REFERENCE)
MAX1167/68 toc08
ANALOG SUPPLY CURRENT vs. ANALOG SUPPLY VOLTAGE (EXTERNAL REFERENCE)
DVDD = +5V fS = 200ksps TA = +85C TA = +70C
MAX1167/68 toc09
3.0 2.5 SUPPLY CURRENT (mA) 2.0 1.5 1.0 0.5 0 -0.5 0 IAVDD, INT REF IAVDD, EXT REF IDVDD DVDD = AVDD = +5V DOUT = ALL ZEROS EXTERNAL CLOCK SPI MODE
2.95 DVDD = +5V fS = 200ksps 2.90 TA = +70C
2.00
TA = +85C
1.95
IAVDD (mA)
IAVDD (mA)
2.85
1.90
2.80 TA = +25C 2.75 TA = 0C TA = -40C 2.70 4.75 4.85 4.95 5.05 5.15 5.25 AVDD (V)
1.85 TA = +25C 1.80 TA = 0C TA = -40C 1.75 4.75 4.85 4.95 5.05 5.15 5.25 AVDD (V)
20 40 60 80 100 120 140 160 180 200 CONVERSION RATE (ksps)
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Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters MAX1167/MAX1168
Typical Operating Characteristics (continued)
(AVDD = DVDD = +5V, fSCLK = 4.8MHz, CDOUT = 30pF, external VREF = +4.096V, TA = +25C, unless otherwise noted.)
POWER-DOWN SUPPLY CURRENT vs. AVDD SUPPLY VOLTAGE (INTERNAL REFERENCE)
MAX1167/68 toc10
DIGITAL SUPPLY CURRENT vs. DIGITAL SUPPLY VOLTAGE
2.6 2.2 1.8 IDVDD (mA) 1.4 1.0 0.6 0.2 2.70 3.21 3.72 4.23 4.74 5.25 DVDD (V) AVDD = +5V VIL = 0 VIH = DVDD fS = 200ksps 0.58
POWER-DOWN SUPPLY CURRENT vs. DVDD SUPPLY VOLTAGE (INTERNAL REFERENCE)
1.04 1.03 0.7 AV DVDD = +5V 0.6 1.02 0.5 IAVDD (mA) 0.4 0.3 IDVDD 1.00 0.2 0.1 2.70 3.21 3.72 4.23 4.74 5.25 DVDD (V) 0.99 1.01 IAVDD (mA) IDVDD (A)
MAX1167/68 toc12
MAX1167/68 toc11
1.03
DVDD = +5V 0.57 0.56 IDVDD (A) 0.55 0.54 0.53 0.52 4.75 4.85 4.95 5.05 5.15 5.25 AVDD (V) IDVDD IAVDD
DOUT = 1010...1010 DOUT = 0000...0000
1.02 1.01 1.00 0.99 0.98
IAVDD
SHUTDOWN SUPPLY CURRENT vs. AVDD SUPPLY VOLTAGE (EXTERNAL REFERENCE)
0.58 0.57 0.56 IDVDD (A) 0.55 0.54 0.53 0.52 4.75 4.85 4.95 5.05 5.15 AVDD (V) IDVDD DVDD = +5V IAVDD 0.46 IDVDD (A) IAVDD (nA) 0.42 0.38 0.34 0.30 5.25 0.5 0.4
MAX1167/68 toc13
SHUTDOWN SUPPLY CURRENT vs. DVDD SUPPLY VOLTAGE (EXTERNAL REFERENCE)
0.54 0.50 0.7 AV DVDD = +5V 0.6 0.42 0.41 0.40 IAVDD 0.3 0.2 0.1 2.70 3.21 3.72 4.23 4.74 5.25 DVDD (V) IDVDD 0.39 0.38 0.37 IAVDD (nA) IAVDD (nA)
MAX1167/68 toc14
0.43
POWER-DOWN SUPPLY CURRENT vs. TEMPERATURE (INTERNAL REFERENCE)
0.58 DVDD = AVDD = +5V 0.57 IAVDD 0.56 IDVDD (A) 0.55 IDVDD 0.54 0.53 0.52 -40 -15 10 35 60 85 TEMPERATURE (C) 1.00 0.99 0.98 1.02 IAVDD (mA) IDVDD (A) 1.01 1.03
MAX1167/68 toc15
SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE (EXTERNAL REFERENCE)
0.58 DVDD = AVDD = +5V 0.57 IAVDD 0.56 0.41 0.55 0.54 0.53 0.52 -40 -15 10 35 60 85 TEMPERATURE (C) 0.37 IDVDD 0.43
MAX1167/68 toc16
1.04
0.45
0.39
0.35
8
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Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters
Typical Operating Characteristics (continued)
(AVDD = DVDD = +5V, fSCLK = 4.8MHz, CDOUT = 30pF, external VREF = +4.096V, TA = +25C, unless otherwise noted.)
MAX1167/MAX1168
OFFSET ERROR vs. SUPPLY VOLTAGE
MAX1167/68 toc17
GAIN ERROR vs. SUPPLY VOLTAGE
MAX1167/68 toc18
OFFSET ERROR vs. TEMPERATURE
VREF = +4.096V
MAX1167/68 toc19
200 100 OFFSET ERROR (V) 0 -100 -200 -300 -400 4.75 4.85 4.95 5.05
VREF = +4.096V
0.05 0.04 GAIN ERROR (%FSR) 0.03 0.02 0.01 0 -0.01 -0.02
VREF = +4.096V
200 150 OFFSET ERROR (V) 100 50 0 -50 -100 -150
5.15
5.25
4.75
4.85
4.95
5.05
5.15
5.25
-40
-15
10
35
60
85
AVDD (V)
AVDD (V)
TEMPERATURE (C)
GAIN ERROR vs. TEMPERATURE
MAX1167/68 toc20
CHANNEL-TO-CHANNEL ISOLATION vs. FREQUENCY
MAX1167/68 toc21
INTERNAL +4.096V REFERENCE VOLTAGE vs. ANALOG SUPPLY VOLTAGE
DVDD = +5V 4.100 VREF (V) TA = +70C 4.096 TA = +25C TA = +85C
MAX1167/68 toc22
0
VREF = +4.096V
0 -20 -40 -60 -80
4.104
-0.001 GAIN ERROR (%FSR)
-0.002
-0.003
ISOLATION (dB)
-0.004
4.092 -100 -120 -40 -15 10 35 60 85 0 20 40 60 80 100 TEMPERATURE (C) FREQUENCY (kHz) 4.088 4.75 4.85
TA = -40C
TA = 0C
-0.005
4.95
5.05
5.15
5.25
AVDD (V)
EXTERNAL REFERENCE INPUT CURRENT vs. EXTERNAL REFERENCE VOLTAGE
MAX1167/68 toc23
INTERNAL REFERENCE VOLTAGE vs. REF LOAD
MAX1167/68 toc24
INTERNAL CLOCK CONVERSION TIME (8th RISING SCLK TO FALLING EOC)
8-BIT DATA-TRANSFER MODE 16-BIT DATA-TRANSFER MODE fSCLK = 4.8MHz 39 31 30 20 10 0 6 24 22 17 17 10 12 28 33 46 38 60 53 44
MAX1167/68 toc25
160 140 120 IREF (A) 100 80 60 87.19ksps, INTERNAL CLOCK 40 20 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VAIN = 0 fSCLK = 4.8MHz AVDD = DVDD = +5V
4.5 4.0 3.5 3.0
70 60 50 tCONV(ms) 40
199ksps, EXTERNAL CLOCK
VREF (V)
2.5 2.0 1.5 1.0 0.5 0 fSCLK = 0 INTERNAL REFERENCE MODE LOAD APPLIED TO REF CREF = 1F 0 2 4 6 8 10 12 14
5.5
1
2
3
4
5
6
7
8
VREF (V)
IREF (mA)
NUMBER OF SCAN-MODE CONVERSIONS
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Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters MAX1167/MAX1168
Pin Description
PIN MAX1167 1 MAX1168 3 NAME FUNCTION Serial Data Output. Data changes state on SCLK's falling edge in SPI/QSPI/MICROWIRE mode and on SCLK's rising edge in DSP mode (MAX1168 only). DOUT is high impedance when CS is high. Serial Clock Input. SCLK drives the conversion process in external clock mode and clocks data out. Serial Data Input. Use DIN to communicate with the command/configuration/control register. In SPI/QSPI/MICROWIRE mode, the rising edge of SCLK clocks in data at DIN. In DSP mode, the falling edge of SCLK clocks in data at DIN. End-of-Conversion Output. In internal clock mode, a logic low at EOC signals the end of a conversion with the result available at DOUT. In external clock mode, EOC remains high. Analog Input 0 Analog Input 1 Analog Input 2 Analog Input 3 Reference Voltage Input/Output. VREF sets the analog voltage range. Bypass to AGND with a 10F capacitor. Bypass with a 1F (min) capacitor when using internal reference. Reference Bypass Capacitor Connection. Bypass to AGND with a 0.1F capacitor when using internal reference. Internal reference and buffer shut down in external reference mode. Analog Ground. Connect to pin 18 (MAX1168) or pin 12 (MAX1167). Primary Analog Ground (Star Ground). Power return for AVDD. Analog Supply Voltage. Bypass to AGND with a 0.1F capacitor. Active-Low Chip-Select Input. Forcing CS high places the MAX1167/MAX1168 in shutdown with a typical supply current of 0.6A. In SPI/QSPI/MICROWIRE mode, a high-to-low transition on CS activates normal operating mode. In DSP mode, after the initial CS transition from high to low, CS can remain low for the entire conversion process (see the Operating Modes section). Digital Ground Digital Supply Voltage. Bypass to DGND with a 0.1F capacitor. DSP Frame-Sync Receive Input. A frame-sync pulse received at DSPR initiates a conversion. Connect to logic high when using SPI/QSPI/MICROWIRE mode. Data-Bit Transfer-Select Input. Logic low on DSEL places the device in 8-bit-wide datatransfer mode. Logic high places the device in 16-bit-wide data-transfer mode. Do not leave DSEL unconnected. Analog Input 4 Analog Input 5
DOUT
2
4
SCLK
3
5
DIN
4 5 6 7 8 9 10 11 12 13
6 7 8 9 10 15 16 17 18 19
EOC AIN0 AIN1 AIN2 AIN3 REF REFCAP AGND AGND AVDD
14
20
CS
15 16 --
21 22 1
DGND DVDD DSPR
--
2
DSEL
-- --
11 12
AIN4 AIN5
10
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Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters
Pin Description (continued)
PIN MAX1167 -- -- -- -- MAX1168 13 14 23 24 NAME AIN6 AIN7 DSPX N.C. Analog Input 6 Analog Input 7 DSP Frame-Sync Transmit Output. A frame-sync pulse at DSPX notifies the DSP that the MSB data is available at DOUT. Leave DSPX unconnected when not in DSP mode. No Connection. Not internally connected. FUNCTION
MAX1167/MAX1168
DVDD 1mA
DOUT DOUT DOUT DOUT
DVDD 1mA
1mA DGND a) VOL TO VOH
CLOAD = 30pF
CLOAD = 30pF DGND b) HIGH-Z TO VOL AND VOH TO VOL
1mA DGND
CLOAD = 30pF
CLOAD = 30pF DGND b) VOL TO HIGH-Z
a) VOH TO HIGH-Z
Figure 1. Load Circuits for DOUT Enable Time and SCLK-toDOUT Delay Time
Figure 2. Load Circuits for DOUT Disable Time
Detailed Description
The MAX1167/MAX1168 low-power, multichannel, 16-bit ADCs feature a successive-approximation ADC, automatic power-down, integrated +4.096V reference, and a high-speed SPI/QSPI/MICROWIRE-compatible interface. A DSPR input and DSPX output allow the MAX1168 to communicate with digital signal processors (DSPs) with no external glue logic. The MAX1167/MAX1168 operate with a single +5V analog supply and feature a separate digital supply, allowing direct interfacing with +2.7V to +5.5V digital logic. Figures 3 and 4 show the functional diagrams of the MAX1167/MAX1168, and Figures 5 and 6 show the MAX1167/MAX1168 in a typical operating circuit. The serial interface simplifies communication with microprocessors (Ps). In external reference mode, the MAX1167/MAX1168 have two power modes: normal mode and shutdown mode. Driving CS high places the MAX1167/MAX1168 in shutdown mode, reducing the supply current to 0.6A (typ). Pull CS low to place the MAX1167/MAX1168 in normal operating mode. The internal reference mode offers software-programmable, power-down options as shown in Table 5.
In SPI/QSPI/MICROWIRE mode, a falling edge on CS wakes the analog circuitry and allows SCLK to clock in data. Acquisition and conversion are initiated by SCLK. The conversion result is available at DOUT in unipolar serial format. DOUT is held low until data becomes available (MSB first) on the 8th falling edge of SCLK when in 8-bit transfer mode, and on the 16th falling edge when in 16-bit transfer mode (see the Operating Modes section). Figure 8 shows the detailed SPI/QSPI/ MICROWIRE serial-interface timing diagram. In external clock mode, the MAX1168 also interfaces with DSPs. In DSP mode, a frame-sync pulse from the DSP initiates a conversion that is driven by SCLK. The MAX1168 formats a frame-sync pulse to notify the DSP that the conversion results are available at DOUT in MSB-first, unipolar, serial-data format. Figure 16 shows the detailed DSP serial-interface timing diagram (see the Operating Modes section).
Analog Input
Figure 7 illustrates the input-sampling architecture of the ADC. The voltage applied at REF or the internal +4.096V reference sets the full-scale input voltage.
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Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters MAX1167/MAX1168
REFCAP AVDD DVDD
REFERENCE REF AGND
BUFFER
MAX1167
AIN0
AIN1 ANALOG-INPUT MULTIPLEXER AIN2 AZ RAIL ANALOG-SWITCH FINE TIMING BIAS DAC COMPARATOR
AIN3
SCLK OSCILLATOR
MULTIPLEXER
SUCCESSIVE-APPROXIMATION REGISTER
OUTPUT
DOUT
ACCUMULATOR CS CONTROL MEMORY EOC
DIN
INPUT REGISTER
AGND
DGND
Figure 3. MAX1167 Functional Diagram
Track/Hold (T/H) In track mode, the analog signal is acquired on the internal hold capacitor. In hold mode, the T/H switches open and the capacitive digital-to-analog converter (DAC) samples the analog input.
During the acquisition, the analog input (AIN_) charges capacitor CDAC. At the end of the acquisition interval the T/H switches open. The retained charge on CDAC represents a sample of the input. In hold mode, the capacitive DAC adjusts during the remainder of the conversion cycle to restore node ZERO to zero within the limits of 16-bit resolution. At the end of the conversion, force CS high and then low to reset the T/H switches back to track mode (AIN_), where CDAC charges to the input signal again.
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The time required for the T/H to acquire an input signal is a function of how quickly its input capacitance is charged. If the input signal's source impedance is high, the acquisition time lengthens and more time must be allowed between conversions. The acquisition time (tACQ) is the maximum time the device takes to acquire the signal. Use the following formula to calculate acquisition time: tACQ = 11(RS + RIN + RDS(ON)) 45pF + 0.3s where R IN = 340, R S = the input signal's source impedance, RDS(ON) = 60, and tACQ is never less than 729ns. A source impedance of less than 200 does not significantly affect the ADC's performance.
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Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters MAX1167/MAX1168
REFCAP AVDD DVDD
REFERENCE REF AGND AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AZ RAIL ANALOG-INPUT MULTIPLEXER
BUFFER
MAX1168
DAC
COMPARATOR
ANALOG-SWITCH FINE TIMING BIAS
SCLK OSCILLATOR
MULTIPLEXER
SUCCESSIVE-APPROXIMATION REGISTER
OUTPUT
DOUT
ACCUMULATOR CS DSEL DSPR MEMORY
CONTROL
EOC DSPX
DIN
INPUT REGISTER
AGND
DGND
Figure 4. MAX1168 Functional Diagram
The MAX1168 features a 16-bit-wide data-transfer mode that includes a longer acquisition time (11.5 clock cycles). Longer acquisition times are useful in applications with input source resistances greater than 1k. Noise increases when using large source resistances. To improve the input signal bandwidth under AC conditions, drive AIN_ with a wideband buffer (>10MHz) that can drive the ADC's input capacitance and settle quickly.
periodic signals with bandwidths exceeding the ADC's sampling rate by using undersampling techniques. To avoid aliasing of unwanted, high-frequency signals into the frequency band of interest, use anti-alias filtering.
Input Bandwidth The ADC's input-tracking circuitry has a 4MHz smallsignal bandwidth, making possible the digitization of high-speed transient events and the measurement of
Analog Input Protection Internal protection diodes, which clamp the analog input to AVDD or AGND, allow the input to swing from (AGND - 0.3V) to (AVDD + 0.3V) without damaging the device. If the analog input exceeds 300mV beyond the supplies, limit the input current to 10mA.
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Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters MAX1167/MAX1168
AIN0 AIN1 AIN2 AIN3 DIN REF 1F +5V 0.1F +5V 0.1F DVDD AVDD AGND AGND DGND REFCAP 0.1F MAX1167
DIN 16 8
CS SCLK DOUT EOC
CS SCLK DOUT EOC
ANALOG INPUTS
ANALOG INPUTS DIN
AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 DIN DSEL DSPR REF 1F MAX1168
CS SCLK DSPX DOUT EOC
CS SCLK DSPX DOUT EOC
+5V 0.1F +5V 0.1F
AVDD
AGND AGND DGND REFCAP 0.1F
DVDD
GND
GND
Figure 5. MAX1167 Typical Operating Circuit
Figure 6. MAX1168 T ypical Operating Circuit
MUX RDSON AIN_ CMUX HOLD CSWITCH TRACK
REF CAPACITIVE DAC ZERO CDAC AGND HOLD TRACK RIN
In addition to the standard 3-wire serial interface modes, the MAX1168 includes a DSPR input and a DSPX output for communicating with DSPs in external clock mode and a DSEL input to determine 8-bit-wide or 16-bit-wide datatransfer mode. When not using the MAX1168 in the DSP interface mode, connect DSPR to DVDD and leave DSPX unconnected.
Command/Configuration/Control Register
AUTOZERO RAIL
Figure 7. Equivalent Input Circuit
Table 1 shows the contents of the command/configuration/control register and the state of each bit after initial power-up. Tables 2-6 define the control and configuration of the device for each bit. Cycling the power supplies resets the command/configuration/control register to the power-on-reset default state.
Digital Interface
The MAX1167/MAX1168 feature an SPI/QSPI/ MICROWIRE-compatible, 3-wire serial interface. The MAX1167 digital interface consists of digital inputs CS, SCLK, and DIN and outputs DOUT and EOC. The MAX1167 operates in the following modes: * SPI interface with external clock * SPI interface with internal clock * SPI interface with internal clock and scan mode
Initialization After Power-Up
A logic high on CS places the MAX1167/MAX1168 in the shutdown mode chosen by the power-down bits, and places DOUT in a high-impedance state. Drive CS low to power up and enable the MAX1167/MAX1168 before starting a conversion. In internal reference mode, allow 5ms for the shutdown internal reference and/or buffer to wake and stabilize before starting a conversion. In external reference mode (or if the internal reference is already on), no reference settling time is needed after power-up.
Table 1. Command/Configuration/Control Register
COMMAND POWER-UP STATE BIT7 (MSB) CH SEL2 0 BIT6 CH SEL1 0 BIT5 CH SEL0 0 BIT4 SCAN1 0 BIT3 SCAN0 0 BIT2 REF/PD_SEL1 1 BIT1 REF/PD SEL0 1 BIT0 (LSB) INT/EXT CLK 0
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Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters MAX1167/MAX1168
Table 2. Channel Select
BIT7 CH SEL2 0 0 0 0 1 1 1 1 BIT6 CH SEL1 0 0 1 1 0 0 1 1 BIT5 CH SEL0 0 1 0 1 0 1 0 1 CHANNEL AIN_ 0 1 2 3 4 5 6 7
Table 3. MAX1167 Scan Mode, Internal Clock Only
ACTION Single channel, no scan Sequentially scan channels 0 through N (N 3) Sequentially scan channels 2 through N (2 N 3) Scan channel N four times BIT4 SCAN1 0 0 1 1 BIT3 SCAN0 0 1 0 1
Table 4. MAX1168 Scan Mode, Internal Clock Only (Not for DSP Mode)
ACTION Single channel, no scan Sequentially scan channels 0 through N (N 7) Sequentially scan channels 4 through N (4 N 7) Scan channel N eight times BIT4 SCAN1 0 0 1 1 BIT3 SCAN0 0 1 0 1
Table 5. Power-Down Modes
BIT2 REF/PD_ SEL1 0 0 1 1 BIT1 REF/PD SEL0 0 1 0 1 REFERENCE REFERENCE MODE (INTERNAL REFERENCE) Internal reference and reference buffer on between conversions Internal reference and reference buffer off between conversions Internal reference on, reference buffer off between conversions Internal reference and buffer always off TYPICAL SUPPLY CURRENT 1mA 0.6A 0.43mA 0.6A TYPICAL WAKEUP TIME (CREF = 1F) NA 5ms 5ms NA
Internal Internal Internal External
Table 6. Clock Modes
BIT0 INT/EXT CLK 0 1 CLOCK MODE External clock Internal clock
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Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters MAX1167/MAX1168
tCSW CS tCSS tCL SCLK tDS tDH DIN tCH *** tCP tCSH
tDO tDV DOUT
tTR
Figure 8. Detailed SPI Interface Timing
CS
when in SPI/QSPI/MICROWIRE mode and on the falling edge of DSPR when in DSP mode. Allow 5ms for the internal reference to rise and settle when powering up from a complete shutdown (VREF = 0, CREF = 1F).
COMPLETE CONVERSION SEQUENCE
DOUT CONVERSION 0 POWERED UP POWERED DOWN CONVERSION 1 POWERED UP
Figure 9. Shutdown Sequence
The internal reference stays on and the buffer is shut off on the rising edge of CS when bit 2 = 1 and bit 1 = 0. The MAX1167/MAX1168 enter this mode on the rising edge of CS. The buffer wakes up on the falling edge of CS when in SPI/QSPI/MICROWIRE mode and on the rising edge of DSPR when in DSP mode. Allow 5ms for VREF to settle when powering up from a complete shutdown (VREF = 0, CREF = 1F). VREFCAP is always equal to +4.096V in this mode. Set both bit 2 and bit 1 to 1 to turn off the reference and reference buffer to allow connection of an external reference. Using an external reference requires no extra wake-up time.
Power-Down Modes
Table 5 shows the MAX1167/MAX1168 power-down modes. Three internal reference modes and one external reference mode are available. Select power-down modes by writing to bits 2 and 1 in the command/configuration/control register. The MAX1167/MAX1168 enter the selected power-down mode on the rising edge of CS. The internal reference stays on when CS is pulled high, if bits 2 and 1 are set to zero. This mode allows for the fastest turn-on time. Setting bit 2 = 0 and bit 1 = 1 turns both the reference and reference buffer off when CS is brought high. This mode achieves the lowest supply current. The reference and buffer wake up on the falling edge of CS
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Operating Modes
External Clock 8-Bit-Wide Data-Transfer Mode (MAX1167 and MAX1168) Force DSPR high and DSEL low (MAX1168) for SPI/ QSPI/MICROWIRE interface mode. The falling edge of CS wakes the analog circuitry and allows SCLK to clock in data. Ensure the duty cycle on SCLK is between 45% and 55% when operating at 4.8MHz (the maximum clock frequency). For lower clock frequencies, ensure the minimum high and low times are at least 93ns. External-clock-mode conversions with
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Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters MAX1167/MAX1168
CS 1 SCLK
MSB LSB 0 MSB LSB
8
16
24
DIN
DOUT
DSPR* DSEL* ADC STATE *MAX1168 ONLY tACQ tCONV IDLE
Figure 10. SPI External Clock Mode, 8-Bit Data-Transfer Mode, Conversion Timing
SCLK rates less than 125kHz can reduce accuracy due to leakage of the sampling capacitor. DOUT changes from high-Z to logic low after CS is brought low. Input data latches on the rising edge of SCLK. The first SCLK rising edge begins loading data into the command/configuration/control register from DIN. The devices select the proper channel for conversion on the rising edge of the 3rd SCLK cycle. Acquisition begins immediately thereafter and ends on the falling edge of the 6th clock cycle. The MAX1167/MAX1168 sample the input and begin conversion on the falling edge of the 6th clock cycle. Setup and configuration of the MAX1167/MAX1168 complete on the rising edge of the 8th clock cycle. The conversion result is available (MSB first) at DOUT on the falling edge of the 8th SCLK cycle. To read the entire conversion result, 16 SCLK cycles are needed. Extra clock pulses, occurring after the conversion result has been clocked out and prior to the rising edge of CS, cause zeros to be clocked out of DOUT. The MAX1167/ MAX1168 external clock 8-bit-wide datatransfer mode requires 24 SCLK cycles for completion (Figure 10). Force CS high after the conversion result is read. For maximum throughput, force CS low again to initiate the next conversion immediately after the specified minimum time (tCSW). Forcing CS high in the middle of a conversion immediately aborts the conversion and places the MAX1167/MAX1168 in shutdown.
External Clock 16-Bit-Wide Data-Transfer Mode (MAX1168 Only) Force DSPR high and DSEL high for SPI/QSPI/ MICROWIRE interface mode. Logic high at DSEL allows the MAX1168 to transfer data in 16-bit-wide words. The acquisition time is extended an extra eight SCLK cycles in the 16-bit-wide data-transfer mode. The falling edge of CS wakes the analog circuitry and allows SCLK to clock in data. Ensure the duty cycle on SCLK is between 45% and 55% when operating at 4.8MHz (the maximum clock frequency). For lower clock frequencies, ensure that the minimum high and low times are at least 93ns. Externalclock-mode conversions with SCLK rates less than 125kHz can reduce accuracy due to leakage of the sampling capacitor. DOUT changes from high-Z to logic low after CS is brought low. Input data latches on the rising edge of SCLK. The first SCLK rising edge begins loading data into the command/configuration/control register from DIN. The devices select the proper channel for conversion and begin acquisition on the rising edge of the 3rd SCLK cycle. Setup and configuration of the MAX1168 completes on the rising edge of the 8th clock cycle. Acquisition ends on the falling edge of the 14th SCLK cycle. The MAX1168 samples the input and begins conversion on the falling edge of the 14th clock cycle. The conversion result is available (MSB first) at DOUT on the falling edge of the 16th SCLK cycle. To read the entire conversion result, 16 SCLK cycles are needed. Extra clock pulses, occurring after the conversion result has been clocked out and prior to the rising edge of CS, cause zeros to be clocked out of DOUT.
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Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters MAX1167/MAX1168
CS 1 SCLK MSB DIN DOUT DSPR DSEL ADC STATE tACQ tCONV IDLE LSB 0X X X X X X X X MSB LSB 8 16 24 32
, X = DON T CARE
Figure 11. SPI External Clock Mode, 16-Bit Data-Transfer Mode, Conversion Timing (MAX1168 Only)
CS 1 SCLK INTERNAL CLK
MSB LSB 1 MSB LSB X
8 2 6 25
9
16
24
DIN DOUT EOC
ADC STATE
, X = DON T CARE DSPR = DVDD, DSEL = GND (MAX1168 ONLY)
tACQ
tCONV
IDLE
POWER-DOWN
Figure 12. SPI Internal Clock Mode, 8-Bit Data-Transfer Mode, Conversion Timing
The MAX1168 external clock 16-bit-wide data-transfer mode requires 32 SCLK cycles for completion (Figure 11). Force CS high after the conversion result is read. For maximum throughput, force CS low again to initiate the next conversion immediately after the specified minimum time (tCSW). Forcing CS high in the middle of a conversion immediately aborts the conversion and places the MAX1168 in shutdown.
Internal Clock 8-Bit-Wide Data-Transfer and Scan Mode (MAX1167 and MAX1168) Force DSPR high and DSEL low (MAX1168) for the SPI/ QSPI/MICROWIRE interface mode. The falling edge of CS wakes the analog circuitry and allows SCLK to clock in data (Figure 12). DOUT changes from high-Z to logic low after CS is brought low. Input data latches on the ris18
ing edge of SCLK. The command/configuration/control register begins reading DIN on the first SCLK rising edge and ends on the rising edge of the 8th SCLK cycle. The MAX1167/MAX1168 select the proper channel for conversion on the rising edge of the 3rd SCLK cycle. The internal oscillator activates 125ns after the rising edge of the 8th SCLK cycle. Turn off the external clock while the internal clock is on. Turning off SCLK ensures the lowest noise performance during acquisition. Acquisition begins on the 2nd rising edge of the internal clock and ends on the falling edge of the 6th internal clock cycle. Each bit of the conversion result shifts into memory as it becomes available. The conversion result is available (MSB first) at DOUT on the falling edge of EOC. The internal oscillator and analog circuitry are shut down on the high-to-low EOC transition. Use the EOC high-to-low transition as the
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Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters MAX1167/MAX1168
CS 1 SCLK 2 INTERNAL CLK DIN DOUT EOC ADC STATE
DATA XXXXXXXX MSB LSB X
8
9
16 13 32
17
24
32
CONFIGURATION , X = DON T CARE DSPR = DSEL = DVDD
tACQ
tCONV
POWER-DOWN
Figure 13. SPI Internal Clock Mode,16-Bit Data-Transfer Mode, Conversion Timing (MAX1168 Only)
CS 1 SCLK INTERNAL CLK
MSB LSB 1 MSB LSB X
8 2 6 24 26 30 48
9
40
DIN DOUT EOC ADC STATE
CONFIGURATION , X = DON T CARE DSPR = DVDD, DSEL = GND (MAX1168 ONLY)
tACQ
tCONV
tACQ
tCONV
POWER-DOWN
Figure 14. SPI Internal Clock Mode, 8-Bit Data-Transfer Mode, Scan Mode for Two Conversions, Conversion Timing
signal to restart the external clock (SCLK). To read the entire conversion result, 16 SCLK cycles are needed. Extra clock pulses, occurring after the conversion result has been clocked out and prior to the rising edge of CS, cause the conversion result to be shifted out again. The MAX1167/MAX1168 internal clock 8-bit-wide datatransfer mode requires 24 external clock cycles and 25 internal clock cycles for completion. Force CS high after the conversion result is read. For maximum throughput, force CS low again to initiate the next conversion immediately after the specified minimum time (tCSW). Forcing CS high in the middle of a conversion immediately aborts the conversion and places the MAX1167/MAX1168 in shutdown.
Scan mode allows multiple channels to be scanned consecutively or one channel to be scanned eight times. Scan mode can only be enabled when using the MAX1167/MAX1168 in the internal clock mode. Enable scanning by setting bits 4 and 3 in the command/configuration/control register (see Tables 3 and 4). In scan mode, conversion results are stored in memory until the completion of the last conversion in the sequence. Upon completion of the last conversion in the sequence, EOC transitions from high to low to indicate the end of the conversion and shuts down the internal oscillator. Use the EOC high-to-low transition as the signal to restart the external clock (SCLK). DOUT provides the conversion results in the same order as the channel conversion process. The MSB of the first conversion is available at DOUT on the falling edge of EOC (Figure 14).
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Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters MAX1167/MAX1168
CS 1 SCLK 2 INTERNAL CLK DIN DOUT EOC ADC STATE
DATA XXXXXXXX MSB LSB X
8
9
16 13 32 34 45 64
17
48
, X = DON T CARE
tACQ
tCONV
tACQ
tCONV
POWER-DOWN
Figure 15. SPI Internal Clock Mode, 16-Bit Data-Transfer Mode, Scan Mode for Two Conversions, Conversion Timing (MAX1168 Only)
tCSW CS tDF tFSS DSPR tFSH tCSS tCL SCLK tCP tDS tDH DIN tCH tCSH
...
...
...
...
tDV DOUT
tDO
tTR
...
Figure 16. Detailed DSP-Interface Timing (MAX1168 Only)
Internal Clock 16-Bit-Wide Data-Transfer and Scan Mode (MAX1168 Only) Force DSPR high and DSEL low for the SPI/QSPI/ MICROWIRE interface mode. The falling edge of CS wakes the analog circuitry and allows SCLK to clock in data (Figure 13). DOUT changes from high-Z to logic low after CS is brought low. Input data latches on the rising edge of SCLK. The command/configuration/control register begins reading DIN on the first SCLK rising edge and ends on the rising edge of the 8th SCLK cycle. The MAX1168 selects the proper channel for
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conversion on the rising edge of the 3rd SCLK cycle. The internal oscillator activates 125ns after the rising edge of the 16th SCLK cycle. Turn off the external clock while the internal clock is on. Turning off SCLK ensures lowest noise performance during acquisition. Acquisition begins on the 2nd rising edge of the internal clock and ends on the falling edge of the 18th internal clock cycle. Each bit of the conversion result shifts into memory as it becomes available. The conversion result is available (MSB first) at DOUT on the falling edge of EOC. The internal oscillator and analog circuitry
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Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters MAX1167/MAX1168
CS
DSPR 1 SCLK
MSB LSB 0 MSB LSB
8
16
24
DIN
DOUT
DSPX
ADC STATE
tACQ
tCONV
IDLE
Figure 17. DSP External Clock Mode, 8-Bit Data-Transfer Mode, Conversion Timing (MAX1168 Only)
CS DSPR 1 SCLK MSB DIN DOUT LSB 0X X X X X X X X MSB LSB 8 16 24 32
DSPX ADC STATE , X = DON T CARE
tACQ
tCONV
IDLE
Figure 18. DSP External Clock Mode, 16-Bit Data-Transfer Mode, Conversion Timing (MAX1168 Only)
are shut down on the EOC high-to-low transition. Use the EOC high-to-low transition as the signal to restart the external clock (SCLK). To read the entire conversion result, 16 SCLK cycles are needed. Extra clock pulses, occurring after the conversion result has been clocked out and prior to the rising edge of CS, cause the conversion result to be shifted out again. The MAX1168 internal-clock 16-bit-wide data-transfer mode requires 32 external clock cycles and 32 internal clock cycles for completion.
Force CS high after the conversion result is read. For maximum throughput, force CS low again to initiate the next conversion immediately after the specified minimum time (tCSW). Forcing CS high in the middle of a conversion immediately aborts the conversion and places the MAX1168 in shutdown. Scan mode allows multiple channels to be scanned consecutively or one channel to be scanned eight times. Scan mode can only be enabled when using the MAX1168 in internal clock mode. Enable scanning by
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Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters
OUTPUT CODE 1111...111 1111...110 1111...101 FULL-SCALE TRANSITION
0000...011 0000...010 0000...001 0000...000 0 1 2 3
FS = VREF V 1 LSB = REF 65,536
FS FS - 3/2 LSB
INPUT VOLTAGE (LSB)
Figure 19. Unipolar Transfer Function, Full Scale (FS) = VREF, Zero Scale (ZS) = GND
rates less than 125kHz can reduce accuracy due to leakage of the sampling capacitor. The input data latches on the falling edge of SCLK. The command/ configuration/control register starts reading data in on the falling edge of the first SCLK cycle immediately following the falling edge of the frame sync pulse and ends on the falling edge of the 8th SCLK cycle. The MAX1168 selects the proper channel for conversion on the falling edge of the 3rd clock cycle and begins acquisition. Acquisition continues until the rising edge of the 7th clock cycle. The MAX1168 samples the input on the rising edge of the 7th clock cycle. On the rising edge of the 8th clock cycle, the MAX1168 outputs a frame sync pulse at DSPX. The frame sync pulse alerts the DSP that the conversion results are about to be output at DOUT (MSB first) starting on the rising edge of the 9th clock pulse. To read the entire conversion result, 16 SCLK cycles are needed. Extra clock pulses, occurring after the conversion result has been clocked out and prior to the next rising edge of DSPR, cause zeros to be clocked out of DOUT. The MAX1168 external clock, DSP 8-bit-wide data-transfer mode requires 24 clock cycles to complete. Begin a new conversion by sending a new frame sync pulse to DSPR followed by new configuration data. Send the new DSPR pulse immediately after reading the conversion result to realize maximum throughput. Sending a new frame sync pulse in the middle of a conversion immediately aborts the current conversion and begins a new one. A rising edge on CS in the middle of a conversion aborts the current conversion and places the MAX1168 in shutdown.
MAX1167/MAX1168
setting bits 4 and 3 in the command/configuration/control register (see Tables 3 and 4). In scan mode, conversion results are stored in memory until the completion of the last conversion in the sequence. Upon completion of the last conversion in the sequence, EOC transitions from high to low to indicate the end of the conversion and shuts down the internal oscillator. Use the EOC high-to-low transition as the signal to restart the external clock (SCLK). DOUT provides the conversion results in the same order as the channel conversion process. The MSB of the first conversion is available at DOUT on the falling edge of EOC. Figure 15 shows the timing diagram for 16-bit-wide data transfer in scan mode.
DSP 8-Bit-Wide Data-Transfer Mode (External Clock Mode, MAX1168 Only) Figure 16 shows the DSP-interface timing diagram. Logic low at DSPR on the falling edge of CS enables DSP interface mode. After the MAX1168 enters DSP mode, CS can remain low for the duration of the conversion process and each subsequent conversion. Drive DSEL low to select the 8-bit data-transfer mode. A sync pulse from the DSP at DSPR wakes the analog circuitry and allows SCLK to clock in data (Figure 17). The frame sync pulse alerts the MAX1168 that incoming data is about to be sent to DIN. Ensure the duty cycle on SCLK is between 45% and 55% when operating at 4.8MHz (the maximum clock frequency). For lower clock frequencies, ensure the minimum high and low times are at least 93ns. External clock mode conversions with SCLK
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DSP 16-Bit-Wide Data-Transfer Mode (External Clock Mode, MAX1168 Only) Figure 16 shows the DSP-interface timing diagram. Logic low at DSPR on the falling edge of CS enables DSP interface mode. After the MAX1168 enters DSP mode, CS can remain low for the duration of the conversion process and each subsequent conversion. The acquisition time is extended an extra eight SCLK cycles in the 16-bit-wide data-transfer mode. Drive DSEL high to select the 16-bit-wide data-transfer mode. A sync pulse from the DSP at DSPR wakes the analog circuitry and allows SCLK to clock in data (Figure 18). The frame sync pulse also alerts the MAX1168 that incoming data is about to be sent to DIN. Ensure the duty cycle on SCLK is between 45% and 55% when operating at 4.8MHz (the maximum clock frequency). For lower clock frequencies, ensure the minimum high and low times are at least 93ns. External-clock-mode conversions with SCLK rates less than 125kHz can reduce accuracy due to leakage of the sampling capacitor.
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Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters MAX1167/MAX1168
I/O SCK MISO SPI VDD CS SCLK DOUT MICROWIRE I/O SK SI CS SCLK DOUT
SS
MAX1167 MAX1168
MAX1167 MAX1168
Figure 20a. SPI Connections
Figure 20b. MICROWIRE Connections
1ST BYTE READ SCLK CS 1 4 6 8
2ND BYTE READ 12 16
DOUT*
0
0
0
0
0
0
0
0
D15 MSB
D14
D13
D12
D11
D10
D9
D8
D7
*WHEN CS IS HIGH, DOUT = HIGH-Z
3RD BYTE READ 20 24
HIGH-Z D7 D6 D5 D4 D3 D2 D1 D0 LSB
Figure 20c. SPI/MICROWIRE Interface Timing Sequence (CPOL = CPHA = 0)
The input data latches on the falling edge of SCLK. The command/configuration/control register starts reading data in on the falling edge of the first SCLK cycle immediately following the falling edge of the frame sync pulse and ends on the falling edge of the 16th SCLK cycle. The MAX1168 selects the proper channel for conversion on the falling edge of the 3rd clock cycle and begins acquisition. Acquisition continues until the rising edge of the 15th clock cycle. The MAX1168 samples the input on the rising edge of the 15th clock cycle. On the rising edge of the 16th clock cycle, the MAX1168 outputs a frame sync pulse at DSPX. The frame sync pulse alerts the DSP that the conversion results are about to be output at DOUT (MSB first) starting on the rising edge of the 17th clock pulse. To read the entire conversion result, 16 SCLK cycles are needed. Extra clock pulses, occurring after the conversion result has been clocked out and prior to the next rising edge of DSPR, cause zeros to be clocked out of DOUT. The MAX1168 external clock, DSP 16-bit-wide data-transfer mode requires 32 clock cycles to complete.
Begin a new conversion by sending a new frame sync pulse to DSPR followed by new configuration data. Send the new DSPR pulse immediately after reading the conversion result to realize maximum throughput. Sending a new frame sync pulse in the middle of a conversion immediately aborts the current conversion and begins a new one. A rising edge on CS in the middle of a conversion aborts the current conversion and places the MAX1168 in shutdown.
Output Coding and Transfer Function
The data output from the MAX1167/MAX1168 is straight binary. Figure 19 shows the nominal transfer function. Code transitions occur halfway between successive integer LSB values (V REF = +4.096V, and 1 LSB = +62.5V or 4.096V / 65,536V).
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Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters MAX1167/MAX1168
Table 7. Detailed SSPCON Register Contents
CONTROL BIT WCOL SSPOV BIT7 BIT6 SETTINGS X X SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPCON) Write Collision Detection Bit Receive Overflow Detection Bit Synchronous Serial-Port Enable Bit: 0: Disables serial port and configures these pins as I/O port pins. 1: Enables serial port and configures SCK, SDO, and SCI pins as serial port pins. Clock Polarity Select Bit. CKP = 0 for SPI master-mode selection. Synchronous Serial-Port Mode Select Bit. Sets SPI master mode and selects fCLK = fOSC / 16.
SSPEN
BIT5
1
CKP SSPM3 SSPM2 SSPM1 SSPM0
BIT4 BIT3 BIT2 BIT1 BIT0
0 0 0 0 1
X = Don't care.
Applications Information
Internal Reference
The internal bandgap reference provides a buffered +4.096V. Bypass REFCAP with a 0.1F capacitor to AGND and REF with a 1F capacitor to AGND. For best results, use low-ESR, X5R/X7R ceramic capacitors. Allow 5ms for the reference and buffer to wake up from full power-down (see Table 5).
When using the internal clock mode, the internal oscillator controls the acquisition and conversion processes, while the external oscillator shifts data in and out of the MAX1167/MAX1168. Turn off the external clock (SCLK) when the internal clock is on to realize lowest noise performance. The internal clock remains off in external clock mode.
Input Buffer
Most applications require an input-buffer amplifier to achieve 16-bit accuracy. The input amplifier must have a slew rate of at least 2V/s and a unity-gain bandwidth of at least 10MHz to complete the required output-voltage change before the end of the acquisition time. At the beginning of the acquisition, the internal sampling capacitor array connects to AIN_ (the amplifier input), causing some disturbance on the output of the buffer. Ensure the sampled voltage has settled before the end of the acquisition time.
External Reference
The MAX1167/MAX1168 accept an external reference with a voltage range between +3.8V and AVDD. Connect the external reference directly to REF. Bypass REF to AGND with a 10F capacitor. When not using a low-ESR bypass capacitor, use a 0.1F ceramic capacitor in parallel with the 10F capacitor. Noise on the reference degrades conversion accuracy. The input impedance at REF is 37k for DC currents. During a conversion, the external reference at REF must deliver 118A of DC load current and have an output impedance of 10 or less. For optimal performance, buffer the reference through an op amp and bypass the REF input. Consider the equivalent input noise (40V RMS ) of the MAX1167/ MAX1168 when choosing a reference.
CS SCK QSPI MISO VDD
CS SCLK DOUT
Internal/External Oscillator
Select either an external (0.1MHz to 4.8MHz) or the internal 4MHz (typ) clock to perform conversions (Table 6). The external clock shifts data in and out of the MAX1167/MAX1168 in either clock mode.
SS
MAX1167 MAX1168
Figure 21a. QSPI Connections
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Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters MAX1167/MAX1168
Table 8. Detailed SSPSTAT Register Contents
CONTROL BIT SMP CKE D/A P S R/W UA BF BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 SETTINGS 0 1 X X X X X X SYNCHRONOUS SERIAL-PORT STATUS REGISTER (SSPSTAT) SPI Data-Input Sample Phase. Input data is sampled at the middle of the data output time. SPI Clock Edge-Select Bit. Data is transmitted on the rising edge of the serial clock. Data Address Bit Stop Bit Start Bit Read/Write Bit Information Update Address Buffer-Full Status Bit
X = Don't care.
SCLK CS DOUT* SAMPLING INSTANT *WHEN CS IS HIGH, DOUT = HIGH-Z
1 4 6 8 12 16 20 24
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
HIGH-Z
MSB
LSB
Figure 21b. QSPI Interface Timing Sequence (External Clock, 8-Bit Data Transfer, CPOL = CPHA = 0)
Digital Noise Digital noise can couple to AIN_ and REF. The conversion clock (SCLK) and other digital signals active during input acquisition contribute noise to the conversion result. Noise signals, synchronous with the sampling interval, result in an effective input offset. Asynchronous signals produce random noise on the input, whose high-frequency components can be aliased into the frequency band of interest. Minimize noise by presenting a low impedance (at the frequencies contained in the noise signal) at the inputs. This requires bypassing AIN_ to AGND, or buffering the input with an amplifier that has a small-signal bandwidth of several megahertz (doing both is preferable). AIN has a typical bandwidth of 4MHz. Distortion Avoid degrading dynamic performance by choosing an amplifier with distortion much less than the total harmonic distortion of the MAX1167/MAX1168 at the frequencies of interest (THD = -100dB at 1kHz). If the chosen amplifier has insufficient common-mode rejection, which results in degraded THD performance, use the inverting configuration (positive input grounded) to eliminate errors from this source. Low-temperaturecoefficient, gain-setting resistors reduce linearity errors caused by resistance changes due to self-heating. To
reduce linearity errors due to finite amplifier gain, use amplifier circuits with sufficient loop gain at the frequencies of interest.
DC Accuracy To improve DC accuracy, choose a buffer with an offset much less than the MAX1167/MAX1168s' offset (10mV max for +5V supply), or whose offset can be trimmed while maintaining stability over the required temperature range.
VDD VDD
SCLK DOUT CS
SCK SDI I/O PIC16/17
MAX1167 MAX1168
GND
Figure 22a. SPI-Interface Connection for a PIC16/PIC17
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Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters MAX1167/MAX1168
1ST BYTE READ SCLK CS 1 4 6 8 2ND BYTE READ 12 16
DOUT*
0
0
0
0
0
0
0
0
D15 MSB
D14
D13
D12
D11
D10
D9
D8
*WHEN CS IS HIGH, DOUT = HIGH-Z
3RD BYTE READ 20 24
HIGH-Z D7 D6 D5 D4 D3 D2 D1 D0 LSB
Figure 22b. SPI Interface Timing with PIC16/PIC17 in Master Mode (CKE = 1, CKP = 0, SMP = 0, SSPM3 - SSPM0 = 0001)
EXTERNAL CLOCK
SCLK TFS RFS DSP DT DR FL1
SCLK DSPR DSPX DIN DOUT CS
QSPI Interface Using the high-speed QSPI interface with CPOL = 0 and CPHA = 0, the MAX1167/MAX1168 support a maximum f SCLK of 4.8MHz. Figure 21a shows the MAX1167/ MAX1168 connected to a QSPI master, and Figure 21b shows the associated interface timing.
MAX1168
PIC16 with SSP Module and PIC17 Interface
The MAX1167/MAX1168 are compatible with a PIC16/PIC17 controller (C), using the synchronous serial-port (SSP) module. To establish SPI communication, connect the controller as shown in Figure 22a and configure the PIC16/PIC17 as system master by initializing its synchronous serialport control register (SSPCON) and synchronous serialport status register (SSPSTAT) to the bit patterns shown in Tables 7 and 8. In SPI mode, the PIC16/PIC17 Cs allow 8 bits of data to be synchronously transmitted and received simultaneously. Three consecutive 8-bit-wide readings (Figure 22b) are necessary to obtain the entire 16-bit result from the ADC. DOUT data transitions on the serial clock's falling edge and is clocked into the C on SCLK's rising edge. The first 8-bit-wide data stream contains all zeros. The 2nd 8-bit-wide data stream contains the MSB through D6. The 3rd 8-bit-wide data stream contains bits D5 through D0 followed by S1 and S0.
Figure 23. DSP Interface Connection
Serial Interfaces
SPI and MICROWIRE Interfaces When using the SPI (Figure 20a) or MICROWIRE (Figure 20b) interfaces, set CPOL = 0 and CPHA = 0. Drive CS low to power on the MAX1167/MAX1168 before starting a conversion (Figure 20c). Three consecutive 8-bit-wide readings are necessary to obtain the entire 16-bit result from the ADC. DOUT data transitions on the serial clock's falling edge. The first 8-bit-wide data stream contains all leading zeros. The 2nd 8-bit-wide data stream contains the MSB through D6. The 3rd 8-bit-wide data stream contains D5 through D0 followed by S1 and S0.
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Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters MAX1167/MAX1168
EFFECTIVE NUMBER OF BITS (ENOB)
16 14 12 EFFECTIVE BITS 10 8 6 4 2 0 0.1 1 fSAMPLE = 200ksps 10 100
AIN_ 1F +5V 0.1F 10
AIN_ REF AVDD
CS SCLK DOUT MAX1167 MAX1168
CS SCLK DOUT
DVDD 0.1F
AGND AGND DGND
FREQUENCY (kHz)
GND
Figure 24. Effective Bits vs. Frequency
Figure 25. Powering AVDD and DVDD from a Single Supply
DSP Interface
The DSP mode of the MAX1168 only operates in external clock mode. Figure 23 shows a typical DSP interface connection to the MAX1168. Use the same oscillator as the DSP to provide the clock signal for the MAX1168. The DSP provides the falling edge at CS to wake the MAX1168. The MAX1168 detects the state of DSPR on the falling edge of CS (Figure 17). Logic low at DSPR places the MAX1168 in DSP mode. After the MAX1168 enters DSP mode, CS can be left low. A frame sync pulse from the DSP to DSPR initiates a conversion. The MAX1168 sends a frame sync pulse from DSPX to the DSP signaling that the MSB is available at DOUT. Send another frame sync pulse from the DSP to DSPR to begin the next conversion. The MAX1168 does not operate in scan mode when using DSP mode.
Aperture Definitions
Aperture jitter (tAJ) is the sample-to-sample variation in the time between samples. Aperture delay (tAD) is the time between the falling edge of the sampling clock and the instant when the actual sample is taken.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (SNR) is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization noise error only and results directly from the ADC's resolution (N bits): SNR = (6.02 N + 1.76)dB In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. The static linearity parameters for the MAX1167/MAX1168 are measured using the end-point method.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the fundamental input frequency's RMS amplitude to the RMS equivalent of all the other ADC output signals: SINAD (dB) = 20 log [SignalRMS / (Noise + Distortion)RMS]
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between an actual step-width and the ideal value of 1 LSB. A DNL error specification of 1 LSB guarantees no missing codes and a monotonic transfer function.
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Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters MAX1167/MAX1168
Effective Number of Bits
Effective number of bits (ENOB) indicates the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC's error consists of quantization noise only. With an input range equal to the fullscale range of the ADC, calculate the ENOB as follows: ENOB = (SINAD - 1.76) / 6.02 Figure 24 shows the ENOB as a function of the MAX1167/MAX1168s' input frequency.
Supplies, Layout, Grounding, and Bypassing
Use printed circuit (PC) boards with separate analog and digital ground planes. Do not use wire-wrap boards. Connect the two ground planes together at the MAX1167/MAX1168 AGND terminal. Isolate the digital supply from the analog with a low-value resistor (10) or ferrite bead when the analog and digital supplies come from the same source (Figure 25). Constraints on sequencing the power supplies and inputs are as follows: * Apply AGND before DGND. * Apply AIN_ and REF after AV DD and AGND are present. * DVDD is independent of the supply sequencing. Ensure that digital return currents do not pass through the analog ground and that return-current paths are low impedance. A 5mA current flowing through a PC board ground trace impedance of only 0.05 creates an error voltage of about 250V and a 4 LSB error with a +4.096V full-scale system. The board layout should ensure that digital and analog signal lines are kept separate. Do not run analog and digital lines (especially the SCLK and DOUT) parallel to one another. If one must cross another, do so at right angles. The ADC's high-speed comparator is sensitive to highfrequency noise on the AVDD power supply. Bypass an excessively noisy supply to the analog ground plane with a 0.1F capacitor in parallel with a 1F to 10F low-ESR capacitor. Keep capacitor leads short for best supply-noise rejection.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS sum of the first five harmonics of the input signal to the fundamental itself. This is expressed as: THD = 20 x log
(V22 + V32 + V42 + V52 )
V1
where V1 is the fundamental amplitude and V2 through V5 are the 2nd- through 5th-order harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest frequency component.
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Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters
Pin Configurations
TOP VIEW
DOUT 1 SCLK 2 DIN 3 EOC 4 AIN0 5 AIN1 6 AIN2 7 AIN3 8 16 DVDD 15 DGND 14 CS DSPR 1 DSEL 2 DOUT 3 SCLK 4 DIN 5 EOC 6 AIN0 7 AIN1 8 AIN2 9 AIN3 10 AIN4 11 AIN5 12 24 N.C. 23 DSPX 22 DVDD 21 DGND
MAX1167/MAX1168
MAX1167
13 AVDD 12 AGND 11 AGND 10 REFCAP 9 REF
MAX1168
20 CS 19 AVDD 18 AGND 17 AGND 16 REFCAP 15 REF 14 AIN7 13 AIN6
QSOP
QSOP
Chip Information
TRANSISTOR COUNT: 20,760 PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 16 QSOP 24 QSOP PACKAGE CODE E16-1 E24-1 DOCUMENT NO. 21-0055
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Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters MAX1167/MAX1168
Revision History
REVISION NUMBER 0 REVISION DATE 8/03 Initial release. Changed 2.9mA at 200ksps to 3.6mA at 200ksps, 1.45mA at 100ksps to 1.85mA at 100ksps, and 145A at 10ksps to 185A to 10ksps in the General Description and Features sections. 1 10/09 Removed the 1.2 INL LSB and 2 INL LSB packages from the Ordering Information table. Updated the Electrical Characteristics table to include the reference buffer and GBD at -40C. DESCRIPTION PAGES CHANGED -- 1
1, 29 2-6
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
30 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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